In the current sub-20 nm technology, three-dimensional (3D) multi-gate devices (FinFETs or Tri-gate devices) are mainstream structures, which improve gate control capability and suppress current leakage and Short Channel Effects (SCEs).
Compared with, for example, conventional single-gate bulk Si or SOI MOSFETs, dual-gate SOI based MOSFETs can suppress the SCEs and the Drain Induced Barrier Lowering (DIBL) effect, have a lower junction capacitance, achieve a lightly-doped channel, adjust a threshold voltage by setting a work function of a metal gate, increase a driving current by a factor of about 2, and reduce the requirement on Equivalent Oxide Thickness (EOT). Compared with the dual-gate devices, the tri-gate devices have a gate surrounding the top surface and both side surfaces of the channel, thereby achieving more powerful gate control capability. Further, all-around nanowire multi-gate devices are more advantageous.
According to an application by the inventor, which has not been disclosed yet, there are provided a FinFET structure and a method for manufacturing the same. The method comprises: etching a bulk Si or SOI substrate to form a plurality of fins and trenches extending in parallel along a first direction; performing ion implantation into or depositing a doped layer and performing annealing on the fins, to form a Punch-Through Stop Layer (PTSL) in the middle of each of the fins to suppress parasitic channel effects; filling the trenches with an insulating material and etching it back to expose a part of each of the fins, to form Shallow Trench Isolation (STI); depositing a thin (only 1-5 nm, for example) dummy gate insulating layer (generally, silicon oxide) on top and side walls of the fins, and depositing a dummy gate layer (generally, polysilicon or amorphous silicon) and a dummy gate cap layer (generally, silicon nitride) on the dummy gate insulating layer; etching the dummy gate layer and the dummy gate insulating layer to form a dummy gate stack extending along a second direction which is preferably perpendicular to the first direction; lightly doping the fins by shallow junction angled implantation at a large tilt angle, diffusion or molecular deposition with the dummy gate stack as a mask to form a Light Doping Drain (LDD) structure, in particular, a Source Drain Extension (SDE) structure, to suppress the DIBL effect; forming a gate spacer on opposite sides of the dummy gate stack in the first direction by deposition and etching; selectively epitaxially growing the same or similar material, preferably SiGe, SiC or the like with higher stress than Si to improve the carrier mobility, on the fins on opposite sides of the gate spacer in the first direction to form source/drain regions (the gate spacer, the top of the dummy gate stack or the like which are made of insulating dielectric materials will not have the semiconductor material grown epitaxially thereon); preferably, forming a Contact Etching Stop Layer (CESL) on the source/drain regions; depositing an Inter-Layer Dielectric (ILD) layer on the wafer; removing the dummy gate stack by etching and leaving a gate trench in the ILD layer; and depositing, in the gate trench, a gate insulating layer of a High-K (HK) material, a gate conductive layer of metal/metal alloy/Metal Nitride (MG), and preferably a gate cap layer of nitride to protect the metal gate. Further, contact holes to the source/drain regions are formed by etching the ILD layer with a mask to expose the source/drain regions. Optionally, metal silicide is formed in the source/drain contact holes to reduce the source/drain contact resistance. Contact plugs are formed by filling the contact holes with metal/metal nitride, preferably metal with a high filling rate such as W, Ti or the like. Due to the existence of the CESL and the gate spacer, the filled metal such as W or Ti will be self-aligned to the source/drain regions, resulting in the contact plugs.
However, the source/drain regions are grown epitaxially after the LDD/SDE implantation process as described above. On one hand, in the implantation process, surfaces of the fins are bombarded with ions driven by an electromagnetic field, with many damages, cracks or the like accumulated therein. These surface defects are disadvantageous for subsequent growth of an epitaxial layer with high quality and low defects, and tend to cause an increase in the source/drain contact resistance (a resistivity is increased due to cracks, gaps or the like on the contact surface), or even result in a failure in the device (in an extreme case, the defects are distributed on the contact surface in a very wide range or very deeply, the epitaxial layer may be stripped in subsequent processes, resulting in disconnection of one or more terminals of the device). On the other hand, the LDD/SDE doped regions formed by the LDD implantation will be subjected to thermal treatment (for example, at 650-1000° C.) for a long time (for example, 5 min-3 h) in the subsequent selective epitaxial growth process, resulting in a serious diffusion of the junction depth and thus serious short channel effects in the device.